module HEARTBEAT_1PPS
#(
    parameter CLK_FREQ = 'd50_000_000
)(
    input CLK,
    input RSTN,
    output HEARTBEAT_OUT
);

reg heartbeat_out;
reg [31:0]counter;

assign HEARTBEAT_OUT = heartbeat_out;

always @(posedge CLK) begin
    if(~RSTN) begin
        heartbeat_out <= 1'b0;
        counter <= 32'd0;
    end
    else begin
        if(counter == (CLK_FREQ / 2 - 'd1)) begin
            counter <= 'd0;
            heartbeat_out <= ~heartbeat_out;
        end
        else begin
            counter <= counter + 'd1;
        end
    end
end
endmodule